1. Field of the Invention
The present invention relates, in general, to arithmetic logic units over a finite field GF (2m) and, more particularly, to an arithmetic logic unit, in which a division algorithm based on a binary greatest common divisor algorithm and a most significant bit-first multiplication algorithm share common logic such as common hardware logic, and both a multiplication and a division can be performed using the shared hardware device.
2. Description of the Related Art
As disclosed in Korean Pat. Appl. No. 1995-22327 (hereinafter referred to as “prior art”), in a conventional multiplication and division unit, a support circuit for multiplication and division operations includes first and second registers for storing input data, a first multiplexer for multiplexing outputs from the second register, an arithmetic logic unit for receiving outputs from the first register and the first multiplexer and arithmetically operating the received outputs in response to an input arithmetic control signal, a shift register capable of reading and writing signals in parallel so as to receive an output from the arithmetic logic unit, perform left and right shifting operations for a multiplication and a division and provide the arithmetic control signal, a gate connected to the arithmetic logic unit so as to gate a negative flag and an overflow flag and output the gated results, and a second multiplexer for receiving and multiplexing the output from the arithmetic logic unit, the output from the gate and the output from the first multiplexer.
However, the prior art is problematic in that the multiplication and division unit of the prior art is divided into structures for performing a multiplication and a division, respectively, and it is not possible to share a single hardware device and perform both a multiplication and a division using the shared hardware device, which are technical characteristics to be accomplished by the present invention.